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| author | Niklas Cassel | 2022-04-14 17:55:10 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-04-22 02:35:16 +0200 |
| commit | d6db2c0fabf979397189aa105d7708be2b433cc4 (patch) | |
| tree | d82993ddbe38ed3c98d3193c9797def296c191ee /include/hw/intc | |
| parent | target/riscv/pmp: fix NAPOT range computation overflow (diff) | |
| download | qemu-d6db2c0fabf979397189aa105d7708be2b433cc4.tar.gz qemu-d6db2c0fabf979397189aa105d7708be2b433cc4.tar.xz qemu-d6db2c0fabf979397189aa105d7708be2b433cc4.zip | |
hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
option is disabled using rv32,mmu=off or rv64,mmu=off.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220414155510.1364147-1-niklas.cassel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/intc')
0 files changed, 0 insertions, 0 deletions