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| author | Leon Alrae | 2016-03-25 14:49:37 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:14:00 +0200 |
| commit | 408294352adb6b38952ada680951f6ed2fd628d6 (patch) | |
| tree | 1acb6b8bc151672d12a7d6354d85b063a99c932a /include/hw/mips | |
| parent | target-mips: make ITC Configuration Tags accessible to the CPU (diff) | |
| download | qemu-408294352adb6b38952ada680951f6ed2fd628d6.tar.gz qemu-408294352adb6b38952ada680951f6ed2fd628d6.tar.xz qemu-408294352adb6b38952ada680951f6ed2fd628d6.zip | |
hw/mips/cps: enable ITU for multithreading processors
Make ITU available in the system if CPU supports multithreading
and is part of CPS.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'include/hw/mips')
| -rw-r--r-- | include/hw/mips/cps.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 88be7653d7..4dbae9c8c9 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "hw/misc/mips_cmgcr.h" #include "hw/misc/mips_cpc.h" +#include "hw/misc/mips_itu.h" #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -37,6 +38,7 @@ typedef struct MIPSCPSState { MemoryRegion container; MIPSGCRState gcr; MIPSCPCState cpc; + MIPSITUState itu; } MIPSCPSState; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); |