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authorYongbok Kim2019-01-03 16:46:32 +0100
committerAleksandar Markovic2019-01-18 16:53:28 +0100
commit043715d1e0fbb3e3411be3f898c5b77b7f90327a (patch)
tree1e92367ebcd199a0e18f4b4233e076299946c440 /include/hw/misc
parenttarget/mips: Add field and R/W access to ITU control register ICR0 (diff)
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target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Update ITU to utilize SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'include/hw/misc')
-rw-r--r--include/hw/misc/mips_itu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 45a0c519b7..c44e7672b6 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -70,6 +70,10 @@ typedef struct MIPSITUState {
/* ITU Control Register */
uint64_t icr0;
+ /* SAAR */
+ bool saar_present;
+ void *saar;
+
} MIPSITUState;
/* Get ITC Configuration Tag memory region. */