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| author | Steven Lee | 2022-05-02 17:03:04 +0200 |
|---|---|---|
| committer | Cédric Le Goater | 2022-05-02 17:03:04 +0200 |
| commit | 5cd7d8564a8b563da724b9e6264c967f0a091afa (patch) | |
| tree | a1258eeba63e0ee45c388d23d12084e436797db6 /include/hw/misc | |
| parent | aspeed/hace: Support HMAC Key Buffer register. (diff) | |
| download | qemu-5cd7d8564a8b563da724b9e6264c967f0a091afa.tar.gz qemu-5cd7d8564a8b563da724b9e6264c967f0a091afa.tar.xz qemu-5cd7d8564a8b563da724b9e6264c967f0a091afa.zip | |
aspeed/hace: Support AST2600 HACE
The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
1. Allocating and initiating accumulative hash digest write buffer
with initial state.
* Since QEMU crypto/hash api doesn't provide the API to set initial
state of hash library, and the initial state is already set by
crypto library (gcrypt/glib/...), so skip this step.
2. Calculating accumulative hash digest.
(a) When receiving the last accumulative data, software need to add
padding message at the end of the accumulative data. Padding
message described in specific of MD5, SHA-1, SHA224, SHA256,
SHA512, SHA512/224, SHA512/256.
* Since the crypto library (gcrypt/glib) already pad the
padding message internally.
* This patch is to remove the padding message which fed byguest
machine driver.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220426021120.28255-3-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/misc')
| -rw-r--r-- | include/hw/misc/aspeed_hace.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index 2242945eb4..40aebf1d6e 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -18,6 +18,7 @@ OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) #define ASPEED_HACE_NR_REGS (0x64 >> 2) +#define ASPEED_HACE_MAX_SG 256 /* max number of entries */ struct AspeedHACEState { SysBusDevice parent; @@ -25,7 +26,10 @@ struct AspeedHACEState { MemoryRegion iomem; qemu_irq irq; + struct iovec iov_cache[ASPEED_HACE_MAX_SG]; uint32_t regs[ASPEED_HACE_NR_REGS]; + uint32_t total_req_len; + uint32_t iov_count; MemoryRegion *dram_mr; AddressSpace dram_as; |