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authorCédric Le Goater2019-09-25 16:32:33 +0200
committerPeter Maydell2019-10-15 19:09:04 +0200
commit8e00d1a97d1d0b416527debb9a0759ab8c49ec51 (patch)
tree818d77b55905ff86e24db9af1b5cd7f04c32167c /include/hw/misc
parentaspeed/timer: Add support for IRQ status register on the AST2600 (diff)
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aspeed/sdmc: Introduce an object class per SoC
Use class handlers and class constants to differentiate the characteristics of the memory controller and remove the 'silicon_rev' property. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc')
-rw-r--r--include/hw/misc/aspeed_sdmc.h19
1 files changed, 15 insertions, 4 deletions
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
index b3c926acae..81156320c4 100644
--- a/include/hw/misc/aspeed_sdmc.h
+++ b/include/hw/misc/aspeed_sdmc.h
@@ -13,6 +13,8 @@
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
+#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
+#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
@@ -24,12 +26,21 @@ typedef struct AspeedSDMCState {
MemoryRegion iomem;
uint32_t regs[ASPEED_SDMC_NR_REGS];
- uint32_t silicon_rev;
- uint32_t ram_bits;
uint64_t ram_size;
uint64_t max_ram_size;
- uint32_t fixed_conf;
-
} AspeedSDMCState;
+#define ASPEED_SDMC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedSDMCClass, (klass), TYPE_ASPEED_SDMC)
+#define ASPEED_SDMC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedSDMCClass, (obj), TYPE_ASPEED_SDMC)
+
+typedef struct AspeedSDMCClass {
+ SysBusDeviceClass parent_class;
+
+ uint64_t max_ram_size;
+ uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
+ void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
+} AspeedSDMCClass;
+
#endif /* ASPEED_SDMC_H */