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| author | Luc Michel | 2020-10-10 15:57:53 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-27 12:10:44 +0100 |
| commit | 957458111280e7772cffc1ccbac75a5270e9267f (patch) | |
| tree | 41c28cc8df093855ecd6389e2fb2de2a0be952fc /include/hw/misc | |
| parent | hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation (diff) | |
| download | qemu-957458111280e7772cffc1ccbac75a5270e9267f.tar.gz qemu-957458111280e7772cffc1ccbac75a5270e9267f.tar.xz qemu-957458111280e7772cffc1ccbac75a5270e9267f.zip | |
hw/misc/bcm2835_cprman: implement PLL channels behaviour
A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc')
0 files changed, 0 insertions, 0 deletions