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| author | Peter Maydell | 2021-05-04 14:09:10 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-05-10 18:21:54 +0200 |
| commit | c52c266d24b10f1482602e6d22938d9e21f874f5 (patch) | |
| tree | a76489a94c7831db08098ea6b2e099bc8d301d21 /include/hw/misc | |
| parent | hw/arm/imx25_pdk: Fix error message for invalid RAM size (diff) | |
| download | qemu-c52c266d24b10f1482602e6d22938d9e21f874f5.tar.gz qemu-c52c266d24b10f1482602e6d22938d9e21f874f5.tar.xz qemu-c52c266d24b10f1482602e6d22938d9e21f874f5.zip | |
hw/misc/mps2-scc: Add "QEMU interface" comment
The MPS2 SCC device doesn't have any documentation of its properties;
add a "QEMU interface" format comment describing them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210504120912.23094-2-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/misc')
| -rw-r--r-- | include/hw/misc/mps2-scc.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index 49d070616a..ea261ea30d 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -9,6 +9,18 @@ * (at your option) any later version. */ +/* + * This is a model of the Serial Communication Controller (SCC) + * block found in most MPS FPGA images. + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + * + QOM property "scc-cfg4": value of the read-only CFG4 register + * + QOM property "scc-aid": value of the read-only SCC_AID register + * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property array "oscclk": reset values of the OSCCLK registers + * (which are accessed via the SYS_CFG channel provided by this device) + */ #ifndef MPS2_SCC_H #define MPS2_SCC_H |