diff options
| author | Peter Maydell | 2021-04-06 14:22:51 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-04-06 14:22:51 +0200 |
| commit | 259e909790c83995436938a2b7af464b5d63d4c3 (patch) | |
| tree | bd6668b5d28b6b2c50e0034ca4c6935296140c4f /include/hw/pci/pcie.h | |
| parent | Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-reque... (diff) | |
| parent | virtio-pci: compat page aligned ATS (diff) | |
| download | qemu-259e909790c83995436938a2b7af464b5d63d4c3.tar.gz qemu-259e909790c83995436938a2b7af464b5d63d4c3.tar.xz qemu-259e909790c83995436938a2b7af464b5d63d4c3.zip | |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc,virtio: last minute bugfixes
Two last minute bugfixes. They are both designed to prevent
compatibility headaches down the road.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Tue 06 Apr 2021 12:13:07 BST
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
virtio-pci: compat page aligned ATS
x86: rename oem-id and oem-table-id properties
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/pci/pcie.h')
| -rw-r--r-- | include/hw/pci/pcie.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 14c58ebdb6..6063bee0ec 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -137,7 +137,7 @@ void pcie_acs_reset(PCIDevice *dev); void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num); -void pcie_ats_init(PCIDevice *dev, uint16_t offset); +void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); |