summaryrefslogtreecommitdiffstats
path: root/include/hw/ppc/spapr.h
diff options
context:
space:
mode:
authorBharata B Rao2016-06-10 02:59:03 +0200
committerDavid Gibson2016-06-17 08:33:49 +0200
commit94a94e4c49197d10e5ee7710bb0538ddeff75ba9 (patch)
tree71449bc46f1b6ef30d4dc237f4d739ebef8af360 /include/hw/ppc/spapr.h
parentspapr: Move spapr_cpu_init() to spapr_cpu_core.c (diff)
downloadqemu-94a94e4c49197d10e5ee7710bb0538ddeff75ba9.tar.gz
qemu-94a94e4c49197d10e5ee7710bb0538ddeff75ba9.tar.xz
qemu-94a94e4c49197d10e5ee7710bb0538ddeff75ba9.zip
spapr: convert boot CPUs into CPU core devices
Introduce sPAPRMachineClass.dr_cpu_enabled to indicate support for CPU core hotplug. Initialize boot time CPUs as core deivces and prevent topologies that result in partially filled cores. Both of these are done only if CPU core hotplug is supported. Note: An unrelated change in the call to xics_system_init() is done in this patch as it makes sense to use the local variable smt introduced in this patch instead of kvmppc_smt_threads() call here. TODO: We derive sPAPR core type by looking at -cpu <model>. However we don't take care of "compat=" feature yet for boot time as well as hotplug CPUs. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc/spapr.h')
-rw-r--r--include/hw/ppc/spapr.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 3277692bff..2a892bddbd 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -38,6 +38,7 @@ struct sPAPRMachineClass {
/*< public >*/
bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
+ bool dr_cpu_enabled; /* enable dynamic-reconfig/hotplug of CPUs */
bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
};
@@ -81,6 +82,7 @@ struct sPAPRMachineState {
/*< public >*/
char *kvm_type;
MemoryHotplugState hotplug_memory;
+ Object **cores;
};
#define H_SUCCESS 0