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author | Cédric Le Goater | 2018-09-11 07:55:02 +0200 |
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committer | David Gibson | 2018-09-25 03:12:25 +0200 |
commit | e39de895f6adc3a274f3116d4f38845d8fcbf135 (patch) | |
tree | 49caf3306ef16c658fc68738fdd87e5787c4d511 /include/hw/ppc/spapr_irq.h | |
parent | 40p: use OR gate to wire up raven PCI interrupts (diff) | |
download | qemu-e39de895f6adc3a274f3116d4f38845d8fcbf135.tar.gz qemu-e39de895f6adc3a274f3116d4f38845d8fcbf135.tar.xz qemu-e39de895f6adc3a274f3116d4f38845d8fcbf135.zip |
spapr: introduce a spapr_irq class 'nr_msis' attribute
The number of MSI interrupts a sPAPR machine can allocate is in direct
relation with the number of interrupts of the sPAPRIrq backend. Define
statically this value at the sPAPRIrq class level and use it for the
"ibm,pe-total-#msi" property of the sPAPR PHB.
According to the PAPR specs, "ibm,pe-total-#msi" defines the maximum
number of MSIs that are available to the PE. We choose to advertise
the maximum number of MSIs that are available to the machine for
simplicity of the model and to avoid segmenting the MSI interrupt pool
which can be easily shared. If the pool limit is reached, it can be
extended dynamically.
Finally, remove XICS_IRQS_SPAPR which is now unused.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc/spapr_irq.h')
-rw-r--r-- | include/hw/ppc/spapr_irq.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 0e98c4474b..650f810ad2 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -31,6 +31,7 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr); typedef struct sPAPRIrq { uint32_t nr_irqs; + uint32_t nr_msis; void (*init)(sPAPRMachineState *spapr, Error **errp); int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp); |