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| author | Cédric Le Goater | 2022-03-02 06:51:39 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2022-03-02 06:51:39 +0100 |
| commit | 623575e16cd55082ca36b57114a774f146b2c95b (patch) | |
| tree | d75205ae6db121b3518f6937eac1722145f044ce /include/hw/ppc | |
| parent | ppc/pnv: Add POWER10 quads (diff) | |
| download | qemu-623575e16cd55082ca36b57114a774f146b2c95b.tar.gz qemu-623575e16cd55082ca36b57114a774f146b2c95b.tar.xz qemu-623575e16cd55082ca36b57114a774f146b2c95b.zip | |
ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor
adjustements in a subclass for P10.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/ppc')
| -rw-r--r-- | include/hw/ppc/pnv.h | 3 | ||||
| -rw-r--r-- | include/hw/ppc/pnv_xscom.h | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 6449fba39b..e5141851fa 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -132,6 +132,9 @@ struct Pnv10Chip { uint32_t nr_quads; PnvQuad *quads; + +#define PNV10_CHIP_MAX_PEC 2 + PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; }; #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 151df15378..75db33d46a 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -137,6 +137,12 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_XIVE2_BASE 0x2010800 #define PNV10_XSCOM_XIVE2_SIZE 0x400 +#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ +#define PNV10_XSCOM_PEC_NEST_SIZE 0x100 + +#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */ +#define PNV10_XSCOM_PEC_PCI_SIZE 0x200 + void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, uint64_t xscom_base, uint64_t xscom_size, |