diff options
| author | Bin Meng | 2019-09-06 18:20:02 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:46 +0200 |
| commit | 20f41c869830fdf0ac9aec8d14b766167f47ce7d (patch) | |
| tree | 81d6ea4c4356d23ae2294e1c98f6f6112b43c31d /include/hw/riscv/sifive_cpu.h | |
| parent | riscv: sifive_e: Drop sifive_mmio_emulate() (diff) | |
| download | qemu-20f41c869830fdf0ac9aec8d14b766167f47ce7d.tar.gz qemu-20f41c869830fdf0ac9aec8d14b766167f47ce7d.tar.xz qemu-20f41c869830fdf0ac9aec8d14b766167f47ce7d.zip | |
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/hw/riscv/sifive_cpu.h')
| -rw-r--r-- | include/hw/riscv/sifive_cpu.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h new file mode 100644 index 0000000000..136799633a --- /dev/null +++ b/include/hw/riscv/sifive_cpu.h @@ -0,0 +1,31 @@ +/* + * SiFive CPU types + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_CPU_H +#define HW_SIFIVE_CPU_H + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif /* HW_SIFIVE_CPU_H */ |