diff options
| author | Bin Meng | 2020-09-01 03:38:57 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:18 +0200 |
| commit | 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330 (patch) | |
| tree | 8976db8de135bd8097e8902b4c261d3988893ee5 /include/hw/riscv | |
| parent | target/riscv: cpu: Add a new 'resetvec' property (diff) | |
| download | qemu-4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330.tar.gz qemu-4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330.tar.xz qemu-4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330.zip | |
hw/riscv: hart: Add a new 'resetvec' property
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/riscv_hart.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index c75856fa73..77aa4bc948 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState { uint32_t num_harts; uint32_t hartid_base; char *cpu_type; + uint64_t resetvec; RISCVCPU *harts; } RISCVHartArrayState; |