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author | Bin Meng | 2020-09-03 12:40:19 +0200 |
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committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
commit | b609b7e3199912e16ef3b0447823f21fed73597e (patch) | |
tree | a4996e2869a356811e641d243f53347b26117106 /include/hw/riscv | |
parent | hw/riscv: Move riscv_htif model to hw/char (diff) | |
download | qemu-b609b7e3199912e16ef3b0447823f21fed73597e.tar.gz qemu-b609b7e3199912e16ef3b0447823f21fed73597e.tar.xz qemu-b609b7e3199912e16ef3b0447823f21fed73597e.zip |
hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
-rw-r--r-- | include/hw/riscv/sifive_uart.h | 77 |
1 files changed, 0 insertions, 77 deletions
diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h deleted file mode 100644 index 65668825a3..0000000000 --- a/include/hw/riscv/sifive_uart.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * SiFive UART interface - * - * Copyright (c) 2016 Stefan O'Rear - * Copyright (c) 2017 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef HW_SIFIVE_UART_H -#define HW_SIFIVE_UART_H - -#include "chardev/char-fe.h" -#include "hw/sysbus.h" - -enum { - SIFIVE_UART_TXFIFO = 0, - SIFIVE_UART_RXFIFO = 4, - SIFIVE_UART_TXCTRL = 8, - SIFIVE_UART_TXMARK = 10, - SIFIVE_UART_RXCTRL = 12, - SIFIVE_UART_RXMARK = 14, - SIFIVE_UART_IE = 16, - SIFIVE_UART_IP = 20, - SIFIVE_UART_DIV = 24, - SIFIVE_UART_MAX = 32 -}; - -enum { - SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */ - SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */ -}; - -enum { - SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */ - SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ -}; - -#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) -#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) - -#define TYPE_SIFIVE_UART "riscv.sifive.uart" - -#define SIFIVE_UART(obj) \ - OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART) - -typedef struct SiFiveUARTState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - qemu_irq irq; - MemoryRegion mmio; - CharBackend chr; - uint8_t rx_fifo[8]; - unsigned int rx_fifo_len; - uint32_t ie; - uint32_t ip; - uint32_t txctrl; - uint32_t rxctrl; - uint32_t div; -} SiFiveUARTState; - -SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, - Chardev *chr, qemu_irq irq); - -#endif |