diff options
| author | Bin Meng | 2020-10-28 06:30:05 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-03 16:17:23 +0100 |
| commit | e35d617919a76b92af799baa483c4ff0e7c090e3 (patch) | |
| tree | fc1c5ad91e365d55bad530875dec4f2c3dbacdbc /include/hw/riscv | |
| parent | hw/misc: Add Microchip PolarFire SoC IOSCB module support (diff) | |
| download | qemu-e35d617919a76b92af799baa483c4ff0e7c090e3.tar.gz qemu-e35d617919a76b92af799baa483c4ff0e7c090e3.tar.xz qemu-e35d617919a76b92af799baa483c4ff0e7c090e3.zip | |
hw/riscv: microchip_pfsoc: Connect the IOSCB module
Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 5b81e26241..a244ae6d39 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -25,6 +25,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" #include "hw/misc/mchp_pfsoc_dmc.h" +#include "hw/misc/mchp_pfsoc_ioscb.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState { DeviceState *plic; MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; MchpPfSoCDdrCfgState ddr_cfg; + MchpPfSoCIoscbState ioscb; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -99,7 +101,7 @@ enum { MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, - MICROCHIP_PFSOC_IOSCB_CFG, + MICROCHIP_PFSOC_IOSCB, MICROCHIP_PFSOC_DRAM, }; |