Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
  hw/riscv: Sort the Kconfig options in alphabetical order
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: sifive_u: Connect a DMA controller
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/dma: Add SiFive platform DMA controller emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/riscv/trace-events

13 files changed, 149 insertions, 642 deletions

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
new file mode 100644
index 0000000000..8bfc7e1a85
--- /dev/null
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -0,0 +1,133 @@
+/*
+ * Microchip PolarFire SoC machine interface
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MICROCHIP_PFSOC_H
+#define HW_MICROCHIP_PFSOC_H
+
+#include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/dma/sifive_pdma.h"
+#include "hw/net/cadence_gem.h"
+#include "hw/sd/cadence_sdhci.h"
+
+typedef struct MicrochipPFSoCState {
+    /*< private >*/
+    DeviceState parent_obj;
+
+    /*< public >*/
+    CPUClusterState e_cluster;
+    CPUClusterState u_cluster;
+    RISCVHartArrayState e_cpus;
+    RISCVHartArrayState u_cpus;
+    DeviceState *plic;
+    MchpPfSoCMMUartState *serial0;
+    MchpPfSoCMMUartState *serial1;
+    MchpPfSoCMMUartState *serial2;
+    MchpPfSoCMMUartState *serial3;
+    MchpPfSoCMMUartState *serial4;
+    SiFivePDMAState dma;
+    CadenceGEMState gem0;
+    CadenceGEMState gem1;
+    CadenceSDHCIState sdhci;
+} MicrochipPFSoCState;
+
+#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
+#define MICROCHIP_PFSOC(obj) \
+    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
+
+typedef struct MicrochipIcicleKitState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+    MicrochipPFSoCState soc;
+} MicrochipIcicleKitState;
+
+#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
+    MACHINE_TYPE_NAME("microchip-icicle-kit")
+#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
+    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
+                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
+
+enum {
+    MICROCHIP_PFSOC_DEBUG,
+    MICROCHIP_PFSOC_E51_DTIM,
+    MICROCHIP_PFSOC_BUSERR_UNIT0,
+    MICROCHIP_PFSOC_BUSERR_UNIT1,
+    MICROCHIP_PFSOC_BUSERR_UNIT2,
+    MICROCHIP_PFSOC_BUSERR_UNIT3,
+    MICROCHIP_PFSOC_BUSERR_UNIT4,
+    MICROCHIP_PFSOC_CLINT,
+    MICROCHIP_PFSOC_L2CC,
+    MICROCHIP_PFSOC_DMA,
+    MICROCHIP_PFSOC_L2LIM,
+    MICROCHIP_PFSOC_PLIC,
+    MICROCHIP_PFSOC_MMUART0,
+    MICROCHIP_PFSOC_SYSREG,
+    MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_EMMC_SD,
+    MICROCHIP_PFSOC_MMUART1,
+    MICROCHIP_PFSOC_MMUART2,
+    MICROCHIP_PFSOC_MMUART3,
+    MICROCHIP_PFSOC_MMUART4,
+    MICROCHIP_PFSOC_GEM0,
+    MICROCHIP_PFSOC_GEM1,
+    MICROCHIP_PFSOC_GPIO0,
+    MICROCHIP_PFSOC_GPIO1,
+    MICROCHIP_PFSOC_GPIO2,
+    MICROCHIP_PFSOC_ENVM_CFG,
+    MICROCHIP_PFSOC_ENVM_DATA,
+    MICROCHIP_PFSOC_IOSCB_CFG,
+    MICROCHIP_PFSOC_DRAM,
+};
+
+enum {
+    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
+    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
+    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
+    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
+    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
+    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
+    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
+    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
+    MICROCHIP_PFSOC_GEM0_IRQ = 64,
+    MICROCHIP_PFSOC_GEM1_IRQ = 70,
+    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
+    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
+    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
+    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
+    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
+    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+};
+
+#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
+#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
+
+#define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
+#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
+#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
+
+#endif /* HW_MICROCHIP_PFSOC_H */
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 9be1fd80ed..ac2cb62e1b 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -39,6 +39,7 @@ struct RISCVHartArrayState {
     uint32_t num_harts;
     uint32_t hartid_base;
     char *cpu_type;
+    uint64_t resetvec;
     RISCVCPU *harts;
 };
 
diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/riscv/riscv_htif.h
deleted file mode 100644
index fb9452cf51..0000000000
--- a/include/hw/riscv/riscv_htif.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * QEMU RISCV Host Target Interface (HTIF) Emulation
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2017-2018 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_RISCV_HTIF_H
-#define HW_RISCV_HTIF_H
-
-#include "chardev/char.h"
-#include "chardev/char-fe.h"
-#include "exec/memory.h"
-#include "target/riscv/cpu.h"
-
-#define TYPE_HTIF_UART "riscv.htif.uart"
-
-typedef struct HTIFState {
-    int allow_tohost;
-    int fromhost_inprogress;
-
-    hwaddr tohost_offset;
-    hwaddr fromhost_offset;
-    uint64_t tohost_size;
-    uint64_t fromhost_size;
-    MemoryRegion mmio;
-    MemoryRegion *address_space;
-    MemoryRegion *main_mem;
-    void *main_mem_ram_ptr;
-
-    CPURISCVState *env;
-    CharBackend chr;
-    uint64_t pending_read;
-} HTIFState;
-
-extern const VMStateDescription vmstate_htif;
-extern const MemoryRegionOps htif_io_ops;
-
-/* HTIF symbol callback */
-void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
-    uint64_t st_size);
-
-/* legacy pre qom */
-HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr);
-
-#endif
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
deleted file mode 100644
index 9f5fb3d31d..0000000000
--- a/include/hw/riscv/sifive_clint.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * SiFive CLINT (Core Local Interruptor) interface
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_CLINT_H
-#define HW_SIFIVE_CLINT_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_CLINT "riscv.sifive.clint"
-
-#define SIFIVE_CLINT(obj) \
-    OBJECT_CHECK(SiFiveCLINTState, (obj), TYPE_SIFIVE_CLINT)
-
-typedef struct SiFiveCLINTState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-    uint32_t hartid_base;
-    uint32_t num_harts;
-    uint32_t sip_base;
-    uint32_t timecmp_base;
-    uint32_t time_base;
-    uint32_t aperture_size;
-} SiFiveCLINTState;
-
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
-    uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
-    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
-
-enum {
-    SIFIVE_SIP_BASE     = 0x0,
-    SIFIVE_TIMECMP_BASE = 0x4000,
-    SIFIVE_TIME_BASE    = 0xBFF8
-};
-
-enum {
-    SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
-};
-
-#endif
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 637414130b..b1400843c2 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -21,7 +21,7 @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
 #define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
deleted file mode 100644
index 698b0b451c..0000000000
--- a/include/hw/riscv/sifive_e_prci.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_E_PRCI_H
-#define HW_SIFIVE_E_PRCI_H
-
-enum {
-    SIFIVE_E_PRCI_HFROSCCFG = 0x0,
-    SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
-    SIFIVE_E_PRCI_PLLCFG    = 0x8,
-    SIFIVE_E_PRCI_PLLOUTDIV = 0xC
-};
-
-enum {
-    SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
-    SIFIVE_E_PRCI_HFROSCCFG_EN  = (1 << 30)
-};
-
-enum {
-    SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
-    SIFIVE_E_PRCI_HFXOSCCFG_EN  = (1 << 30)
-};
-
-enum {
-    SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
-    SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
-    SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
-    SIFIVE_E_PRCI_PLLCFG_LOCK   = (1 << 31)
-};
-
-enum {
-    SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
-};
-
-#define SIFIVE_E_PRCI_REG_SIZE  0x1000
-
-#define TYPE_SIFIVE_E_PRCI      "riscv.sifive.e.prci"
-
-#define SIFIVE_E_PRCI(obj) \
-    OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
-
-typedef struct SiFiveEPRCIState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-    uint32_t hfrosccfg;
-    uint32_t hfxosccfg;
-    uint32_t pllcfg;
-    uint32_t plloutdiv;
-} SiFiveEPRCIState;
-
-DeviceState *sifive_e_prci_create(hwaddr addr);
-
-#endif
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
deleted file mode 100644
index cf12fcfd62..0000000000
--- a/include/hw/riscv/sifive_gpio.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * SiFive System-on-Chip general purpose input/output register definition
- *
- * Copyright 2019 AdaCore
- *
- * Base on nrf51_gpio.c:
- *
- * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
- *
- * This code is licensed under the GPL version 2 or later.  See
- * the COPYING file in the top-level directory.
- */
-
-#ifndef SIFIVE_GPIO_H
-#define SIFIVE_GPIO_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
-#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
-
-#define SIFIVE_GPIO_PINS 32
-
-#define SIFIVE_GPIO_SIZE 0x100
-
-#define SIFIVE_GPIO_REG_VALUE      0x000
-#define SIFIVE_GPIO_REG_INPUT_EN   0x004
-#define SIFIVE_GPIO_REG_OUTPUT_EN  0x008
-#define SIFIVE_GPIO_REG_PORT       0x00C
-#define SIFIVE_GPIO_REG_PUE        0x010
-#define SIFIVE_GPIO_REG_DS         0x014
-#define SIFIVE_GPIO_REG_RISE_IE    0x018
-#define SIFIVE_GPIO_REG_RISE_IP    0x01C
-#define SIFIVE_GPIO_REG_FALL_IE    0x020
-#define SIFIVE_GPIO_REG_FALL_IP    0x024
-#define SIFIVE_GPIO_REG_HIGH_IE    0x028
-#define SIFIVE_GPIO_REG_HIGH_IP    0x02C
-#define SIFIVE_GPIO_REG_LOW_IE     0x030
-#define SIFIVE_GPIO_REG_LOW_IP     0x034
-#define SIFIVE_GPIO_REG_IOF_EN     0x038
-#define SIFIVE_GPIO_REG_IOF_SEL    0x03C
-#define SIFIVE_GPIO_REG_OUT_XOR    0x040
-
-typedef struct SIFIVEGPIOState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion mmio;
-
-    qemu_irq irq[SIFIVE_GPIO_PINS];
-    qemu_irq output[SIFIVE_GPIO_PINS];
-
-    uint32_t value;             /* Actual value of the pin */
-    uint32_t input_en;
-    uint32_t output_en;
-    uint32_t port;              /* Pin value requested by the user */
-    uint32_t pue;
-    uint32_t ds;
-    uint32_t rise_ie;
-    uint32_t rise_ip;
-    uint32_t fall_ie;
-    uint32_t fall_ip;
-    uint32_t high_ie;
-    uint32_t high_ip;
-    uint32_t low_ie;
-    uint32_t low_ip;
-    uint32_t iof_en;
-    uint32_t iof_sel;
-    uint32_t out_xor;
-    uint32_t in;
-    uint32_t in_mask;
-
-    /* config */
-    uint32_t ngpio;
-} SIFIVEGPIOState;
-
-#endif /* SIFIVE_GPIO_H */
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
deleted file mode 100644
index ace76d0f1b..0000000000
--- a/include/hw/riscv/sifive_plic.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SiFive PLIC (Platform Level Interrupt Controller) interface
- *
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This provides a RISC-V PLIC device
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_PLIC_H
-#define HW_SIFIVE_PLIC_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
-
-#define SIFIVE_PLIC(obj) \
-    OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC)
-
-typedef enum PLICMode {
-    PLICMode_U,
-    PLICMode_S,
-    PLICMode_H,
-    PLICMode_M
-} PLICMode;
-
-typedef struct PLICAddr {
-    uint32_t addrid;
-    uint32_t hartid;
-    PLICMode mode;
-} PLICAddr;
-
-typedef struct SiFivePLICState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-    uint32_t num_addrs;
-    uint32_t num_harts;
-    uint32_t bitfield_words;
-    PLICAddr *addr_config;
-    uint32_t *source_priority;
-    uint32_t *target_priority;
-    uint32_t *pending;
-    uint32_t *claimed;
-    uint32_t *enable;
-
-    /* config */
-    char *hart_config;
-    uint32_t hartid_base;
-    uint32_t num_sources;
-    uint32_t num_priorities;
-    uint32_t priority_base;
-    uint32_t pending_base;
-    uint32_t enable_base;
-    uint32_t enable_stride;
-    uint32_t context_base;
-    uint32_t context_stride;
-    uint32_t aperture_size;
-} SiFivePLICState;
-
-DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
-    uint32_t hartid_base, uint32_t num_sources,
-    uint32_t num_priorities, uint32_t priority_base,
-    uint32_t pending_base, uint32_t enable_base,
-    uint32_t enable_stride, uint32_t context_base,
-    uint32_t context_stride, uint32_t aperture_size);
-
-#endif
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
deleted file mode 100644
index 1ec416ac1b..0000000000
--- a/include/hw/riscv/sifive_test.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * QEMU Test Finisher interface
- *
- * Copyright (c) 2018 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_TEST_H
-#define HW_SIFIVE_TEST_H
-
-#include "hw/sysbus.h"
-
-#define TYPE_SIFIVE_TEST "riscv.sifive.test"
-
-#define SIFIVE_TEST(obj) \
-    OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST)
-
-typedef struct SiFiveTestState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-} SiFiveTestState;
-
-enum {
-    FINISHER_FAIL = 0x3333,
-    FINISHER_PASS = 0x5555,
-    FINISHER_RESET = 0x7777
-};
-
-DeviceState *sifive_test_create(hwaddr addr);
-
-#endif
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d3c0c00d10..fe5c580845 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,12 +19,13 @@
 #ifndef HW_SIFIVE_U_H
 #define HW_SIFIVE_U_H
 
+#include "hw/dma/sifive_pdma.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_prci.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/gpio/sifive_gpio.h"
+#include "hw/misc/sifive_u_otp.h"
+#include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
@@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState {
     SiFiveUPRCIState prci;
     SIFIVEGPIOState gpio;
     SiFiveUOTPState otp;
+    SiFivePDMAState dma;
     CadenceGEMState gem;
 
     uint32_t serial;
@@ -72,6 +74,7 @@ enum {
     SIFIVE_U_MROM,
     SIFIVE_U_CLINT,
     SIFIVE_U_L2CC,
+    SIFIVE_U_PDMA,
     SIFIVE_U_L2LIM,
     SIFIVE_U_PLIC,
     SIFIVE_U_PRCI,
@@ -108,6 +111,14 @@ enum {
     SIFIVE_U_GPIO_IRQ13 = 20,
     SIFIVE_U_GPIO_IRQ14 = 21,
     SIFIVE_U_GPIO_IRQ15 = 22,
+    SIFIVE_U_PDMA_IRQ0 = 23,
+    SIFIVE_U_PDMA_IRQ1 = 24,
+    SIFIVE_U_PDMA_IRQ2 = 25,
+    SIFIVE_U_PDMA_IRQ3 = 26,
+    SIFIVE_U_PDMA_IRQ4 = 27,
+    SIFIVE_U_PDMA_IRQ5 = 28,
+    SIFIVE_U_PDMA_IRQ6 = 29,
+    SIFIVE_U_PDMA_IRQ7 = 30,
     SIFIVE_U_GEM_IRQ = 0x35
 };
 
diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h
deleted file mode 100644
index 639297564a..0000000000
--- a/include/hw/riscv/sifive_u_otp.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * QEMU SiFive U OTP (One-Time Programmable) Memory interface
- *
- * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_U_OTP_H
-#define HW_SIFIVE_U_OTP_H
-
-#define SIFIVE_U_OTP_PA         0x00
-#define SIFIVE_U_OTP_PAIO       0x04
-#define SIFIVE_U_OTP_PAS        0x08
-#define SIFIVE_U_OTP_PCE        0x0C
-#define SIFIVE_U_OTP_PCLK       0x10
-#define SIFIVE_U_OTP_PDIN       0x14
-#define SIFIVE_U_OTP_PDOUT      0x18
-#define SIFIVE_U_OTP_PDSTB      0x1C
-#define SIFIVE_U_OTP_PPROG      0x20
-#define SIFIVE_U_OTP_PTC        0x24
-#define SIFIVE_U_OTP_PTM        0x28
-#define SIFIVE_U_OTP_PTM_REP    0x2C
-#define SIFIVE_U_OTP_PTR        0x30
-#define SIFIVE_U_OTP_PTRIM      0x34
-#define SIFIVE_U_OTP_PWE        0x38
-
-#define SIFIVE_U_OTP_PCE_EN     (1 << 0)
-
-#define SIFIVE_U_OTP_PDSTB_EN   (1 << 0)
-
-#define SIFIVE_U_OTP_PTRIM_EN   (1 << 0)
-
-#define SIFIVE_U_OTP_PA_MASK        0xfff
-#define SIFIVE_U_OTP_NUM_FUSES      0x1000
-#define SIFIVE_U_OTP_SERIAL_ADDR    0xfc
-
-#define SIFIVE_U_OTP_REG_SIZE       0x1000
-
-#define TYPE_SIFIVE_U_OTP           "riscv.sifive.u.otp"
-
-#define SIFIVE_U_OTP(obj) \
-    OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP)
-
-typedef struct SiFiveUOTPState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-    uint32_t pa;
-    uint32_t paio;
-    uint32_t pas;
-    uint32_t pce;
-    uint32_t pclk;
-    uint32_t pdin;
-    uint32_t pdstb;
-    uint32_t pprog;
-    uint32_t ptc;
-    uint32_t ptm;
-    uint32_t ptm_rep;
-    uint32_t ptr;
-    uint32_t ptrim;
-    uint32_t pwe;
-    uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES];
-    /* config */
-    uint32_t serial;
-} SiFiveUOTPState;
-
-#endif /* HW_SIFIVE_U_OTP_H */
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
deleted file mode 100644
index 0a531fdadc..0000000000
--- a/include/hw/riscv/sifive_u_prci.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
- *
- * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_U_PRCI_H
-#define HW_SIFIVE_U_PRCI_H
-
-#define SIFIVE_U_PRCI_HFXOSCCFG     0x00
-#define SIFIVE_U_PRCI_COREPLLCFG0   0x04
-#define SIFIVE_U_PRCI_DDRPLLCFG0    0x0C
-#define SIFIVE_U_PRCI_DDRPLLCFG1    0x10
-#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
-#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
-#define SIFIVE_U_PRCI_CORECLKSEL    0x24
-#define SIFIVE_U_PRCI_DEVICESRESET  0x28
-#define SIFIVE_U_PRCI_CLKMUXSTATUS  0x2C
-
-/*
- * Current FU540-C000 manual says ready bit is at bit 29, but
- * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
- * We have to trust the actual code that works.
- *
- * see https://github.com/sifive/freedom-u540-c000-bootloader
- */
-
-#define SIFIVE_U_PRCI_HFXOSCCFG_EN  (1 << 30)
-#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
-
-/* xxxPLLCFG0 register bits */
-#define SIFIVE_U_PRCI_PLLCFG0_DIVR  (1 << 0)
-#define SIFIVE_U_PRCI_PLLCFG0_DIVF  (31 << 6)
-#define SIFIVE_U_PRCI_PLLCFG0_DIVQ  (3 << 15)
-#define SIFIVE_U_PRCI_PLLCFG0_FSE   (1 << 25)
-#define SIFIVE_U_PRCI_PLLCFG0_LOCK  (1 << 31)
-
-/* xxxPLLCFG1 register bits */
-#define SIFIVE_U_PRCI_PLLCFG1_CKE   (1 << 24)
-
-/* coreclksel register bits */
-#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK  (1 << 0)
-
-
-#define SIFIVE_U_PRCI_REG_SIZE  0x1000
-
-#define TYPE_SIFIVE_U_PRCI      "riscv.sifive.u.prci"
-
-#define SIFIVE_U_PRCI(obj) \
-    OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
-
-typedef struct SiFiveUPRCIState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    MemoryRegion mmio;
-    uint32_t hfxosccfg;
-    uint32_t corepllcfg0;
-    uint32_t ddrpllcfg0;
-    uint32_t ddrpllcfg1;
-    uint32_t gemgxlpllcfg0;
-    uint32_t gemgxlpllcfg1;
-    uint32_t coreclksel;
-    uint32_t devicesreset;
-    uint32_t clkmuxstatus;
-} SiFiveUPRCIState;
-
-/*
- * Clock indexes for use by Device Tree data and the PRCI driver.
- *
- * These values are from sifive-fu540-prci.h in the Linux kernel.
- */
-#define PRCI_CLK_COREPLL        0
-#define PRCI_CLK_DDRPLL         1
-#define PRCI_CLK_GEMGXLPLL      2
-#define PRCI_CLK_TLCLK          3
-
-#endif /* HW_SIFIVE_U_PRCI_H */
diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h
deleted file mode 100644
index 65668825a3..0000000000
--- a/include/hw/riscv/sifive_uart.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * SiFive UART interface
- *
- * Copyright (c) 2016 Stefan O'Rear
- * Copyright (c) 2017 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef HW_SIFIVE_UART_H
-#define HW_SIFIVE_UART_H
-
-#include "chardev/char-fe.h"
-#include "hw/sysbus.h"
-
-enum {
-    SIFIVE_UART_TXFIFO        = 0,
-    SIFIVE_UART_RXFIFO        = 4,
-    SIFIVE_UART_TXCTRL        = 8,
-    SIFIVE_UART_TXMARK        = 10,
-    SIFIVE_UART_RXCTRL        = 12,
-    SIFIVE_UART_RXMARK        = 14,
-    SIFIVE_UART_IE            = 16,
-    SIFIVE_UART_IP            = 20,
-    SIFIVE_UART_DIV           = 24,
-    SIFIVE_UART_MAX           = 32
-};
-
-enum {
-    SIFIVE_UART_IE_TXWM       = 1, /* Transmit watermark interrupt enable */
-    SIFIVE_UART_IE_RXWM       = 2  /* Receive watermark interrupt enable */
-};
-
-enum {
-    SIFIVE_UART_IP_TXWM       = 1, /* Transmit watermark interrupt pending */
-    SIFIVE_UART_IP_RXWM       = 2  /* Receive watermark interrupt pending */
-};
-
-#define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
-#define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
-
-#define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-#define SIFIVE_UART(obj) \
-    OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
-
-typedef struct SiFiveUARTState {
-    /*< private >*/
-    SysBusDevice parent_obj;
-
-    /*< public >*/
-    qemu_irq irq;
-    MemoryRegion mmio;
-    CharBackend chr;
-    uint8_t rx_fifo[8];
-    unsigned int rx_fifo_len;
-    uint32_t ie;
-    uint32_t ip;
-    uint32_t txctrl;
-    uint32_t rxctrl;
-    uint32_t div;
-} SiFiveUARTState;
-
-SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
-    Chardev *chr, qemu_irq irq);
-
-#endif