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| author | Philippe Mathieu-Daudé | 2019-02-02 20:48:46 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2019-11-05 23:33:12 +0100 |
| commit | 0063454affb3c5a595539a3cad9e20e7229d8fac (patch) | |
| tree | bf75d84bb022448a3994237b64a827b028b7d352 /include/hw/southbridge | |
| parent | hw/pci-host/piix: Extract piix3_create() (diff) | |
| download | qemu-0063454affb3c5a595539a3cad9e20e7229d8fac.tar.gz qemu-0063454affb3c5a595539a3cad9e20e7229d8fac.tar.xz qemu-0063454affb3c5a595539a3cad9e20e7229d8fac.zip | |
hw/pci-host/piix: Move RCR_IOPORT register definition
The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h", and prepend the PIIX prefix.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Diffstat (limited to 'include/hw/southbridge')
| -rw-r--r-- | include/hw/southbridge/piix.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index add352456b..e49d4a6bbe 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +/* + * Reset Control Register: PCI-accessible ISA-Compatible Register at address + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). + */ +#define PIIX_RCR_IOPORT 0xcf9 + extern PCIDevice *piix4_dev; DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, |