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| author | Peter Maydell | 2016-06-17 17:16:37 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-06-17 17:16:37 +0200 |
| commit | 482b61844ae7c6df39df0b48ac90ffbc87bed7d2 (patch) | |
| tree | f3344170f132d6c8f01e4693496a37827b654c15 /include/hw/timer/aspeed_timer.h | |
| parent | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-pull-request' int... (diff) | |
| parent | ACPI: ARM: Present GIC version in MADT table (diff) | |
| download | qemu-482b61844ae7c6df39df0b48ac90ffbc87bed7d2.tar.gz qemu-482b61844ae7c6df39df0b48ac90ffbc87bed7d2.tar.xz qemu-482b61844ae7c6df39df0b48ac90ffbc87bed7d2.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160617' into staging
target-arm queue:
* GICv3 emulation
# gpg: Signature made Fri 17 Jun 2016 15:24:28 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20160617: (22 commits)
ACPI: ARM: Present GIC version in MADT table
hw/timer: Add value matching support to aspeed_timer
target-arm/monitor.c: Advertise emulated GICv3 in capabilities
target-arm/machine.c: Allow user to request GICv3 emulation
hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers
hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
hw/intc/arm_gicv3: Implement gicv3_set_irq()
hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions
hw/intc/arm_gicv3: Implement GICv3 redistributor registers
hw/intc/arm_gicv3: Implement GICv3 distributor registers
hw/intc/arm_gicv3: Implement functions to identify next pending irq
hw/intc/arm_gicv3: ARM GICv3 device framework
hw/intc/arm_gicv3: Add vmstate descriptors
hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure
hw/intc/arm_gicv3: Add state information
target-arm: Add mp-affinity property for ARM CPU class
target-arm: Provide hook to tell GICv3 about changes of security state
target-arm: Define new arm_is_el3_or_mon() function
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/timer/aspeed_timer.h')
| -rw-r--r-- | include/hw/timer/aspeed_timer.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h index 44dc2f89d5..bd6c1a7f96 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -22,7 +22,7 @@ #ifndef ASPEED_TIMER_H #define ASPEED_TIMER_H -#include "hw/ptimer.h" +#include "qemu/timer.h" #define ASPEED_TIMER(obj) \ OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER); @@ -33,15 +33,16 @@ typedef struct AspeedTimer { qemu_irq irq; uint8_t id; + QEMUTimer timer; /** * Track the line level as the ASPEED timers implement edge triggered * interrupts, signalling with both the rising and falling edge. */ int32_t level; - ptimer_state *timer; uint32_t reload; uint32_t match[2]; + uint64_t start; } AspeedTimer; typedef struct AspeedTimerCtrlState { |