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| author | Alistair Francis | 2021-08-30 07:34:49 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-09-20 23:56:49 +0200 |
| commit | e5cc6aaeb51dd0d80e1f5a6d6a6808d6355958aa (patch) | |
| tree | f4cea728c25c7f0d734a49ed04de9d88314aa110 /include/hw/timer/ibex_timer.h | |
| parent | hw/intc: sifive_clint: Use RISC-V CPU GPIO lines (diff) | |
| download | qemu-e5cc6aaeb51dd0d80e1f5a6d6a6808d6355958aa.tar.gz qemu-e5cc6aaeb51dd0d80e1f5a6d6a6808d6355958aa.tar.xz qemu-e5cc6aaeb51dd0d80e1f5a6d6a6808d6355958aa.zip | |
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'include/hw/timer/ibex_timer.h')
0 files changed, 0 insertions, 0 deletions