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| author | Aleksandr Bezzubikov | 2017-08-18 01:36:49 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2017-09-08 15:15:17 +0200 |
| commit | 226263fb5cdaa4a4a95f1680fabbc9dd2123fd67 (patch) | |
| tree | 0f6cb5ffb56205bc2a73f85362c53bd2ac77a6a4 /include/hw | |
| parent | hw/pci: introduce bridge-only vendor-specific capability to provide some hint... (diff) | |
| download | qemu-226263fb5cdaa4a4a95f1680fabbc9dd2123fd67.tar.gz qemu-226263fb5cdaa4a4a95f1680fabbc9dd2123fd67.tar.xz qemu-226263fb5cdaa4a4a95f1680fabbc9dd2123fd67.zip | |
hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port
To enable hotplugging of a newly created pcie-pci-bridge,
we need to tell firmware (e.g. SeaBIOS) to reserve
additional buses or IO/MEM/PREF space for pcie-root-port.
Additional bus reservation allows us to hotplug pcie-pci-bridge into this root port.
The number of buses and IO/MEM/PREF space to reserve are provided to the device via
a corresponding property, and to the firmware via new PCI capability.
The properties' default values are -1 to keep default behavior unchanged.
Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Tested-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/pci/pcie_port.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 13332668e8..0736014bfd 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -65,6 +65,7 @@ void pcie_chassis_del_slot(PCIESlot *s); typedef struct PCIERootPortClass { PCIDeviceClass parent_class; + DeviceRealize parent_realize; uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); |