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| author | Peter Maydell | 2021-08-12 11:33:32 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-09-01 12:08:18 +0200 |
| commit | 2f9db77ea8330db9d038603055e0543512365283 (patch) | |
| tree | eb8850a1bcf7d1aca9a8f30e2a6a38ca305b4f5c /include/hw | |
| parent | tests/arm-cpu-features: Add A64FX processor related tests (diff) | |
| download | qemu-2f9db77ea8330db9d038603055e0543512365283.tar.gz qemu-2f9db77ea8330db9d038603055e0543512365283.tar.xz qemu-2f9db77ea8330db9d038603055e0543512365283.zip | |
arm: Move M-profile RAS register block into its own device
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into memory at the right
address.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/armv7m.h | 2 | ||||
| -rw-r--r-- | include/hw/intc/armv7m_nvic.h | 1 | ||||
| -rw-r--r-- | include/hw/misc/armv7m_ras.h | 37 |
3 files changed, 39 insertions, 1 deletions
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index bc6733c518..4cae0d7eea 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -12,6 +12,7 @@ #include "hw/sysbus.h" #include "hw/intc/armv7m_nvic.h" +#include "hw/misc/armv7m_ras.h" #include "target/arm/idau.h" #include "qom/object.h" @@ -58,6 +59,7 @@ struct ARMv7MState { NVICState nvic; BitBandState bitband[ARMV7M_NUM_BITBANDS]; ARMCPU *cpu; + ARMv7MRAS ras; /* MemoryRegion we pass to the CPU, with our devices layered on * top of the ones the board provides in board_memory. diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 39c71e1593..33b6d8810c 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,7 +83,6 @@ struct NVICState { MemoryRegion sysreg_ns_mem; MemoryRegion systickmem; MemoryRegion systick_ns_mem; - MemoryRegion ras_mem; MemoryRegion container; MemoryRegion defaultmem; diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h new file mode 100644 index 0000000000..ba6daccf3f --- /dev/null +++ b/include/hw/misc/armv7m_ras.h @@ -0,0 +1,37 @@ +/* + * Arm M-profile RAS (Reliability, Availability and Serviceability) block + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the RAS register block of an M-profile CPU + * (the registers starting at 0xE0005000 with ERRFRn). + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + * + * The QEMU implementation currently provides "minimal RAS" only. + */ + +#ifndef HW_MISC_ARMV7M_RAS_H +#define HW_MISC_ARMV7M_RAS_H + +#include "hw/sysbus.h" + +#define TYPE_ARMV7M_RAS "armv7m-ras" +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS) + +struct ARMv7MRAS { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; +}; + +#endif |