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author | Beniamino Galvani | 2014-03-25 19:22:06 +0100 |
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committer | Peter Maydell | 2014-04-17 22:34:06 +0200 |
commit | 323a8771cfb96ab752c9d27e939a2fbac1380b1c (patch) | |
tree | bd2059a391b50b27945adacb1057022121461e2a /include/hw | |
parent | allwinner-a10-pic: fix behaviour of pending register (diff) | |
download | qemu-323a8771cfb96ab752c9d27e939a2fbac1380b1c.tar.gz qemu-323a8771cfb96ab752c9d27e939a2fbac1380b1c.tar.xz qemu-323a8771cfb96ab752c9d27e939a2fbac1380b1c.zip |
allwinner-a10-pit: avoid generation of spurious interrupts
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1395771730-16882-4-git-send-email-b.galvani@gmail.com
[PMM: avoid duplicate typedef of AwA10PITState]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r-- | include/hw/timer/allwinner-a10-pit.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index 15efab8b5f..2158fc0d7b 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -35,12 +35,20 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 -typedef struct AwA10PITState { +typedef struct AwA10PITState AwA10PITState; + +typedef struct AwA10TimerContext { + AwA10PITState *container; + int index; +} AwA10TimerContext; + +struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ qemu_irq irq[AW_A10_PIT_TIMER_NR]; ptimer_state * timer[AW_A10_PIT_TIMER_NR]; + AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; MemoryRegion iomem; uint32_t irq_enable; @@ -53,6 +61,6 @@ typedef struct AwA10PITState { uint32_t count_lo; uint32_t count_hi; uint32_t count_ctl; -} AwA10PITState; +}; #endif |