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| author | Peter Maydell | 2021-02-19 15:45:55 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:02 +0100 |
| commit | 3378873802afe8af0355c4fac3e11e6510fc1f27 (patch) | |
| tree | 563fa01a7eb193e21f97c54937c2325f004b1ae5 /include/hw | |
| parent | hw/arm/armsse: Use an array for apb_ppc fields in the state structure (diff) | |
| download | qemu-3378873802afe8af0355c4fac3e11e6510fc1f27.tar.gz qemu-3378873802afe8af0355c4fac3e11e6510fc1f27.tar.xz qemu-3378873802afe8af0355c4fac3e11e6510fc1f27.zip | |
hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
The SSE uses 32 interrupts for its own devices, and then passes through
its expansion IRQ inputs to the CPU's interrupts 33 and upward.
Add a define for the number of IRQs the SSE uses for itself, instead
of hardcoding 32.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-23-peter.maydell@linaro.org
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/armsse.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 771150b0a9..e34263fed8 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -145,6 +145,9 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, #define RAM3_PPU 6 #define NUM_PPUS 7 +/* Number of CPU IRQs used by the SSE itself */ +#define NUM_SSE_IRQS 32 + struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -165,7 +168,7 @@ struct ARMSSE { qemu_or_irq mpc_irq_orgate; qemu_or_irq nmi_orgate; - SplitIRQ cpu_irq_splitter[32]; + SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; CMSDKAPBDualTimer dualtimer; |