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| author | Bin Meng | 2020-09-03 12:40:16 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 406fafd5d0f9a1c6a365ff1733c26a043b1c4877 (patch) | |
| tree | ee4ed77217e62a3d3a8c185e8eda59ff2a138c35 /include/hw | |
| parent | hw/riscv: Move sifive_gpio model to hw/gpio (diff) | |
| download | qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.tar.gz qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.tar.xz qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.zip | |
hw/riscv: Move sifive_clint model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/intc/sifive_clint.h (renamed from include/hw/riscv/sifive_clint.h) | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h index a30be0f3d6..a30be0f3d6 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/intc/sifive_clint.h |