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| author | Alistair Francis | 2020-05-13 19:42:46 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-06-19 17:24:07 +0200 |
| commit | 5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1 (patch) | |
| tree | cf6ea7f11f5f0aafdc450287a2e4cbfc14acc1aa /include/hw | |
| parent | riscv: Add helper to make NaN-boxing for FP register (diff) | |
| download | qemu-5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1.tar.gz qemu-5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1.tar.xz qemu-5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1.zip | |
sifive_e: Support the revB machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/sifive_e.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d386ea9223..637414130b 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -45,6 +45,7 @@ typedef struct SiFiveEState { /*< public >*/ SiFiveESoCState soc; + bool revb; } SiFiveEState; #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") |