diff options
| author | Cédric Le Goater | 2016-10-22 11:46:38 +0200 |
|---|---|---|
| committer | David Gibson | 2016-10-28 00:38:25 +0200 |
| commit | 631adaff31d9e127fecccb4a811c20ae13cd7194 (patch) | |
| tree | f1b9498ab9ca86aede63c40d2ccd7149923a340c /include/hw | |
| parent | ppc/pnv: add a core mask to PnvChip (diff) | |
| download | qemu-631adaff31d9e127fecccb4a811c20ae13cd7194.tar.gz qemu-631adaff31d9e127fecccb4a811c20ae13cd7194.tar.xz qemu-631adaff31d9e127fecccb4a811c20ae13cd7194.zip | |
ppc/pnv: add a PIR handler to PnvChip
The Processor Identification Register (PIR) is a register that holds a
processor identifier which is used for bus transactions (XSCOM) and
for processor differentiation in multiprocessor systems. It also used
in the interrupt vector entries (IVE) to identify the thread serving
the interrupts.
P9 and P8 have some differences in the CPU PIR encoding.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/ppc/pnv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index e084a8c303..b7987f8208 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -58,6 +58,8 @@ typedef struct PnvChipClass { PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; + + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" |