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| author | Bin Meng | 2020-09-01 03:38:58 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:18 +0200 |
| commit | 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 (patch) | |
| tree | b8e8f5ca6ba769ca3ac776411be5f2d75d72781b /include/hw | |
| parent | hw/riscv: hart: Add a new 'resetvec' property (diff) | |
| download | qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.tar.gz qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.tar.xz qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.zip | |
target/riscv: cpu: Set reset vector based on the configured property value
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
0 files changed, 0 insertions, 0 deletions