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authorBin Meng2019-09-06 18:20:03 +0200
committerPalmer Dabbelt2019-09-17 17:42:46 +0200
commit91c985851dd57df3b003e7bd91f1cf544b3a288d (patch)
treee6ffda5ae64dec6db9d71b5bdfaf3f55c62deb98 /include/hw
parentriscv: Add a sifive_cpu.h to include both E and U cpu type defines (diff)
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riscv: hart: Extract hart realize to a separate routine
Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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