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| author | Peter Maydell | 2015-09-08 18:38:42 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-09-08 18:38:42 +0200 |
| commit | b06c262b45cf7afcf56dd0f2189ad8948b117e7d (patch) | |
| tree | 406180418657b11461ab30f72b547426ecdd0797 /include/hw | |
| parent | target-microblaze: Use setcond for pcmp* (diff) | |
| download | qemu-b06c262b45cf7afcf56dd0f2189ad8948b117e7d.tar.gz qemu-b06c262b45cf7afcf56dd0f2189ad8948b117e7d.tar.xz qemu-b06c262b45cf7afcf56dd0f2189ad8948b117e7d.zip | |
armv7m_nvic: Implement ICSR without using internal GIC state
Change the implementation of the Interrupt Control and State Register
in the v7M NVIC to not use the running_irq and last_active internal
state fields in the GIC. These fields don't correspond to state in
a real GIC and will be removed soon.
The changes to the ICSR are:
* the VECTACTIVE field is documented as identical to the IPSR[8:0]
field, so implement it that way
* implement RETTOBASE via looking at the active state bits
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1438089748-5528-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/hw')
0 files changed, 0 insertions, 0 deletions