diff options
| author | Alistair Francis | 2021-03-31 17:00:11 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:02:06 +0200 |
| commit | d4cad544992225105d88c3d744bce1b08947dd24 (patch) | |
| tree | 64fbfe4e098d81844b0d22bc4b0e7fb71a2211c8 /include/hw | |
| parent | MAINTAINERS: Update the RISC-V CPU Maintainers (diff) | |
| download | qemu-d4cad544992225105d88c3d744bce1b08947dd24.tar.gz qemu-d4cad544992225105d88c3d744bce1b08947dd24.tar.xz qemu-d4cad544992225105d88c3d744bce1b08947dd24.zip | |
hw/opentitan: Update the interrupt layout
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/opentitan.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index a5ea3a5e4e..aab9bc9245 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -82,14 +82,14 @@ enum { }; enum { - IBEX_UART_RX_PARITY_ERR_IRQ = 0x28, - IBEX_UART_RX_TIMEOUT_IRQ = 0x27, - IBEX_UART_RX_BREAK_ERR_IRQ = 0x26, - IBEX_UART_RX_FRAME_ERR_IRQ = 0x25, - IBEX_UART_RX_OVERFLOW_IRQ = 0x24, - IBEX_UART_TX_EMPTY_IRQ = 0x23, - IBEX_UART_RX_WATERMARK_IRQ = 0x22, - IBEX_UART_TX_WATERMARK_IRQ = 0x21, + IBEX_UART0_RX_PARITY_ERR_IRQ = 8, + IBEX_UART0_RX_TIMEOUT_IRQ = 7, + IBEX_UART0_RX_BREAK_ERR_IRQ = 6, + IBEX_UART0_RX_FRAME_ERR_IRQ = 5, + IBEX_UART0_RX_OVERFLOW_IRQ = 4, + IBEX_UART0_TX_EMPTY_IRQ = 3, + IBEX_UART0_RX_WATERMARK_IRQ = 2, + IBEX_UART0_TX_WATERMARK_IRQ = 1, }; #endif |