diff options
| author | Vitaly Wool | 2020-11-12 08:49:51 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:43 +0100 |
| commit | dfc973ecc1e8a2c148c0011be89c012891f72384 (patch) | |
| tree | b7dadff9110e592b3c11bbed0dbeb724b599131d /include/hw | |
| parent | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB (diff) | |
| download | qemu-dfc973ecc1e8a2c148c0011be89c012891f72384.tar.gz qemu-dfc973ecc1e8a2c148c0011be89c012891f72384.tar.xz qemu-dfc973ecc1e8a2c148c0011be89c012891f72384.zip | |
hw/riscv: microchip_pfsoc: add QSPI NOR flash
Add QSPI NOR flash definition for Microchip PolarFire SoC.
Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 51d44637db..d0c666aae0 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -97,6 +97,8 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_SPI0, + MICROCHIP_PFSOC_SPI1, MICROCHIP_PFSOC_I2C1, MICROCHIP_PFSOC_GEM0, MICROCHIP_PFSOC_GEM1, @@ -105,6 +107,7 @@ enum { MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, + MICROCHIP_PFSOC_QSPI_XIP, MICROCHIP_PFSOC_IOSCB, MICROCHIP_PFSOC_DRAM_LO, MICROCHIP_PFSOC_DRAM_LO_ALIAS, |