diff options
| author | Bin Meng | 2019-09-06 18:20:05 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:47 +0200 |
| commit | f3d47d580402d11b73108de807031124c135e370 (patch) | |
| tree | 9a5ee2ca12cd58f0a0c64669b8f6bfbf7585b7c1 /include/hw | |
| parent | riscv: hart: Add a "hartid-base" property to RISC-V hart array (diff) | |
| download | qemu-f3d47d580402d11b73108de807031124c135e370.tar.gz qemu-f3d47d580402d11b73108de807031124c135e370.tar.xz qemu-f3d47d580402d11b73108de807031124c135e370.zip | |
riscv: sifive_u: Set the minimum number of cpus to 2
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index f25bad8f13..6d227410f8 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,6 +69,8 @@ enum { SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; +#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 |