diff options
| author | Richard Braun | 2018-02-22 16:12:51 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-02-22 16:12:51 +0100 |
| commit | f6bfe45af2a9bd1b929955ca3bf54726d1e68d88 (patch) | |
| tree | 192a87b7baeb70244561b22df6442fbda77eebf4 /include/hw | |
| parent | raspi: Add "raspi3" machine type (diff) | |
| download | qemu-f6bfe45af2a9bd1b929955ca3bf54726d1e68d88.tar.gz qemu-f6bfe45af2a9bd1b929955ca3bf54726d1e68d88.tar.xz qemu-f6bfe45af2a9bd1b929955ca3bf54726d1e68d88.zip | |
hw/char/stm32f2xx_usart: fix TXE/TC bit handling
I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.
In addition, fix the reset value of the USART status register.
Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
[PMM: removed XXX tag from comment, since it isn't something
we need to come back and fix in QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/char/stm32f2xx_usart.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/hw/char/stm32f2xx_usart.h b/include/hw/char/stm32f2xx_usart.h index 9d03a7527c..84c4029777 100644 --- a/include/hw/char/stm32f2xx_usart.h +++ b/include/hw/char/stm32f2xx_usart.h @@ -37,7 +37,12 @@ #define USART_CR3 0x14 #define USART_GTPR 0x18 -#define USART_SR_RESET 0x00C00000 +/* + * NB: The reset value mentioned in "24.6.1 Status register" seems bogus. + * Looking at "Table 98 USART register map and reset values", it seems it + * should be 0xc0, and that's how real hardware behaves. + */ +#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC) #define USART_SR_TXE (1 << 7) #define USART_SR_TC (1 << 6) |