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| author | Aurelien Jarno | 2015-07-14 17:45:16 +0200 |
|---|---|---|
| committer | Leon Alrae | 2015-07-15 15:07:25 +0200 |
| commit | 908680c6441ac468f4871d513f42be396ea0d264 (patch) | |
| tree | 859583452660338766188f7f8dd438fabcc8774e /include/standard-headers/linux | |
| parent | linux-user: Fix MIPS N64 trap and break instruction bug (diff) | |
| download | qemu-908680c6441ac468f4871d513f42be396ea0d264.tar.gz qemu-908680c6441ac468f4871d513f42be396ea0d264.tar.xz qemu-908680c6441ac468f4871d513f42be396ea0d264.zip | |
target-mips: fix page fault address for LWL/LWR/LDL/LDR
When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU
currently reports the aligned address in CP0 BadVAddr, while the Windows
NT kernel expects the unaligned address.
This patch adds a byte access with the unaligned address at the
beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page
fault and fill the QEMU TLB.
Cc: Leon Alrae <leon.alrae@imgtec.com>
Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'include/standard-headers/linux')
0 files changed, 0 insertions, 0 deletions