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| author | Peter Maydell | 2016-12-22 20:23:51 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-12-22 20:23:51 +0100 |
| commit | a470b33259bf82ef2336bfcd5d07640562d3f63b (patch) | |
| tree | d86ac1e104302269c73ecac2e6540fc299934e7f /include/standard-headers/linux | |
| parent | Merge remote-tracking branch 'remotes/berrange/tags/pull-qcrypto-2016-12-21-2... (diff) | |
| parent | x86: implement la57 paging mode (diff) | |
| download | qemu-a470b33259bf82ef2336bfcd5d07640562d3f63b.tar.gz qemu-a470b33259bf82ef2336bfcd5d07640562d3f63b.tar.xz qemu-a470b33259bf82ef2336bfcd5d07640562d3f63b.zip | |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* core support for MemoryRegionCache from myself
* rules.mak speedup and cleanups from myself and Marc-Adnré
* multiboot command line fix from Vlad
* SCSI fixes from myself
* small qemu-timer speedup from myself
* x86 debugging improvements from Doug
* configurable Q35 devices from Chao
* x86 5-level paging support from Kirill
* x86 SHA_NI support for KVM from Yi Sun
* improved kvmclock migration logic from Marcelo
* bugfixes and doc fixes from others
# gpg: Signature made Thu 22 Dec 2016 15:01:13 GMT
# gpg: using RSA key 0xBFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream: (25 commits)
x86: implement la57 paging mode
target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns
kvmclock: reduce kvmclock difference on migration
kvm: sync linux headers
scsi-disk: fix VERIFY for scsi-block
hw/block/pflash_cfi*.c: fix confusing assert fail message
multiboot: copy the cmdline verbatim, unescape module strings
x86: Fix x86_64 'g' packet response to gdb from 32-bit mode.
pc: make pit configurable
pc: make sata configurable
pc: make smbus configurable
target-i386: Add Intel SHA_NI instruction support.
block: drop remaining legacy aio functions in comment
main-loop: update comment for qemu_mutex_lock/unlock_iothread
timer: fix misleading comment in timer.h
qemu-timer: check active_timers outside lock/event
virtio-scsi: introduce virtio_scsi_acquire/release
build-sys: remove libtool left-over
rules.mak: add more rules to avoid chaining
rules.mak: speedup save-vars load-vars
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/standard-headers/linux')
| -rw-r--r-- | include/standard-headers/linux/input.h | 1 | ||||
| -rw-r--r-- | include/standard-headers/linux/pci_regs.h | 15 |
2 files changed, 15 insertions, 1 deletions
diff --git a/include/standard-headers/linux/input.h b/include/standard-headers/linux/input.h index 7361a16b50..b472b8530c 100644 --- a/include/standard-headers/linux/input.h +++ b/include/standard-headers/linux/input.h @@ -245,6 +245,7 @@ struct input_mask { #define BUS_SPI 0x1C #define BUS_RMI 0x1D #define BUS_CEC 0x1E +#define BUS_INTEL_ISHTP 0x1F /* * MT_TOOL types diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index 404095124a..e5a2e68b22 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -612,6 +612,8 @@ */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ +#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ +#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */ #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ @@ -619,6 +621,7 @@ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ +#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ @@ -671,7 +674,8 @@ #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DPC +#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 @@ -964,4 +968,13 @@ #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ +/* Precision Time Measurement */ +#define PCI_PTM_CAP 0x04 /* PTM Capability */ +#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ +#define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ +#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ +#define PCI_PTM_CTRL 0x08 /* PTM Control */ +#define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ +#define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ + #endif /* LINUX_PCI_REGS_H */ |