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| author | Peter Maydell | 2016-01-21 15:15:09 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-01-21 15:15:09 +0100 |
| commit | 03fbf20f4da58f41998dc10ec7542f65d37ba759 (patch) | |
| tree | 7fb7c5695aad485d9a3a3830177493afb9c704ee /include | |
| parent | target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode (diff) | |
| download | qemu-03fbf20f4da58f41998dc10ec7542f65d37ba759.tar.gz qemu-03fbf20f4da58f41998dc10ec7542f65d37ba759.tar.xz qemu-03fbf20f4da58f41998dc10ec7542f65d37ba759.zip | |
target-arm: Implement FPEXC32_EL2 system register
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3,
and allows those exception levels to read and write the FPEXC
register for a lower exception level that is using AArch32.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1453132414-8127-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions