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author | Alistair Francis | 2020-05-13 19:37:08 +0200 |
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committer | Alistair Francis | 2020-06-03 18:11:51 +0200 |
commit | 0869490b1cc4d917ac4eb3a02cac7d71149def91 (patch) | |
tree | b0ee6cbea827562c00d57835ef1b34774e5ea9db /include | |
parent | docs: deprecated: Update the -bios documentation (diff) | |
download | qemu-0869490b1cc4d917ac4eb3a02cac7d71149def91.tar.gz qemu-0869490b1cc4d917ac4eb3a02cac7d71149def91.tar.xz qemu-0869490b1cc4d917ac4eb3a02cac7d71149def91.zip |
riscv: sifive_e: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/riscv/sifive_e.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 25ce7aa9d5..414992119e 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -47,6 +47,10 @@ typedef struct SiFiveEState { SiFiveESoCState soc; } SiFiveEState; +#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") +#define RISCV_E_MACHINE(obj) \ + OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE) + enum { SIFIVE_E_DEBUG, SIFIVE_E_MROM, |