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| author | Leon Alrae | 2016-03-25 14:49:36 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:14:00 +0200 |
| commit | 0d74a222c27e26fc40f4f6120c61c3f9ceaa3776 (patch) | |
| tree | c2b00f3e999a86c58ff15eb43ce07421d1b90b25 /include | |
| parent | target-mips: check CP0 enabled for CACHE instruction also in R6 (diff) | |
| download | qemu-0d74a222c27e26fc40f4f6120c61c3f9ceaa3776.tar.gz qemu-0d74a222c27e26fc40f4f6120c61c3f9ceaa3776.tar.xz qemu-0d74a222c27e26fc40f4f6120c61c3f9ceaa3776.zip | |
target-mips: make ITC Configuration Tags accessible to the CPU
Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv
processors these bits are used to enable CACHE instruction access to
different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will
access ITC tag values.
Generally we do not model caches and we have been treating the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions