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| author | Peter Maydell | 2020-11-19 22:56:11 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:56 +0100 |
| commit | 0e83f905fb043cedb0282f77b97c50292e148faa (patch) | |
| tree | 17bee91c698cfcca8a9c7c3fb008d80e2eae8dc4 /include | |
| parent | target/arm: Implement new v8.1M VLLDM and VLSTM encodings (diff) | |
| download | qemu-0e83f905fb043cedb0282f77b97c50292e148faa.tar.gz qemu-0e83f905fb043cedb0282f77b97c50292e148faa.tar.xz qemu-0e83f905fb043cedb0282f77b97c50292e148faa.zip | |
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions