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author | Max Filippov | 2013-02-17 13:38:58 +0100 |
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committer | Max Filippov | 2019-01-28 20:55:20 +0100 |
commit | 10df8ff146ff0219cf746ac13ffa870c4cf0350a (patch) | |
tree | 78dc8fcc630a6659520a2542375f84eab84d7e0b /include | |
parent | target/xtensa: expose core runstall as an IRQ line (diff) | |
download | qemu-10df8ff146ff0219cf746ac13ffa870c4cf0350a.tar.gz qemu-10df8ff146ff0219cf746ac13ffa870c4cf0350a.tar.xz qemu-10df8ff146ff0219cf746ac13ffa870c4cf0350a.zip |
target/xtensa: add MX interrupt controller
MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
corresponding external IRQ pin of selected subset of connected xtensa
cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
combination of 3 designated external IRQ pins of connected xtensa
cores;
- cache coherecy register controls core L1 cache participation in the
SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/xtensa/mx_pic.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/include/hw/xtensa/mx_pic.h b/include/hw/xtensa/mx_pic.h new file mode 100644 index 0000000000..e6cd8cf016 --- /dev/null +++ b/include/hw/xtensa/mx_pic.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _XTENSA_MX_PIC_H +#define _XTENSA_MX_PIC_H + +#include "exec/memory.h" +#include "hw/irq.h" + +struct XtensaMxPic; +typedef struct XtensaMxPic XtensaMxPic; + +XtensaMxPic *xtensa_mx_pic_init(unsigned n_extint); +void xtensa_mx_pic_reset(void *opaque); +MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx, + qemu_irq *irq, + qemu_irq runstall); +qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx); + +#endif |