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| author | Richard Henderson | 2020-06-26 05:31:08 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-06-26 15:31:12 +0200 |
| commit | 21a8b343eaae63f6984f9a200092b0ea167647f1 (patch) | |
| tree | 22aa7f8b971043464a7f04952b93563866bdef55 /include | |
| parent | target/arm: Implement the IRG instruction (diff) | |
| download | qemu-21a8b343eaae63f6984f9a200092b0ea167647f1.tar.gz qemu-21a8b343eaae63f6984f9a200092b0ea167647f1.tar.xz qemu-21a8b343eaae63f6984f9a200092b0ea167647f1.zip | |
target/arm: Revise decoding for disas_add_sub_imm
The current Arm ARM has adjusted the official decode of
"Add/subtract (immediate)" so that the shift field is only bit 22,
and bit 23 is part of the op1 field of the parent category
"Data processing - immediate".
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-11-richard.henderson@linaro.org
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions