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| author | Peter Maydell | 2022-01-07 18:07:59 +0100 |
|---|---|---|
| committer | Peter Maydell | 2022-01-07 18:07:59 +0100 |
| commit | 257bb6501cda75e9ba0804cd5b45e17275928252 (patch) | |
| tree | 6bebe2b90e15867d8651da1f762d18ee650437e8 /include | |
| parent | hw/intc/arm_gicv3_its: Use FIELD macros for DTEs (diff) | |
| download | qemu-257bb6501cda75e9ba0804cd5b45e17275928252.tar.gz qemu-257bb6501cda75e9ba0804cd5b45e17275928252.tar.xz qemu-257bb6501cda75e9ba0804cd5b45e17275928252.zip | |
hw/intc/arm_gicv3_its: Correct comment about CTE RDBase field size
The comment says that in our CTE format the RDBase field is 36 bits;
in fact for us it is only 16 bits, because we use the RDBase format
where it specifies a 16-bit CPU number. The code already uses
RDBASE_PROCNUM_LENGTH (16) as the field width, so fix the comment
to match it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions
