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authorLeon Alrae2015-09-14 14:51:31 +0200
committerLeon Alrae2015-10-29 17:16:44 +0100
commit2dcf7908d9e0274c08911400beb7ed14276bb170 (patch)
tree31852b7fb89257870cb1ce5a96e9f703183efb72 /include
parenttarget-mips: implement the CPU wake-up on non-enabled interrupts in R6 (diff)
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target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
Implement the relationship between CP0.Status.KX, SX and UX. It should not be possible to set UX bit if SX is 0, the same applies for setting SX if KX is 0. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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