diff options
| author | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
| commit | 2ecf17264debe1bc3399fe587690c78d03e8401b (patch) | |
| tree | 792d6d3331647aff8e0d1e5a587b240bcb0d19dc /include | |
| parent | hw/arm: ast2600: Correct the iBT interrupt ID (diff) | |
| download | qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.gz qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.tar.xz qemu-2ecf17264debe1bc3399fe587690c78d03e8401b.zip | |
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/aspeed_soc.h | 2 | ||||
| -rw-r--r-- | include/hw/misc/aspeed_lpc.h | 32 |
2 files changed, 34 insertions, 0 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 11cfe6e358..42c64bd28b 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -28,6 +28,7 @@ #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" +#include "hw/misc/aspeed_lpc.h" #define ASPEED_SPIS_NUM 2 #define ASPEED_EHCIS_NUM 2 @@ -61,6 +62,7 @@ struct AspeedSoCState { AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; + AspeedLPCState lpc; }; #define TYPE_ASPEED_SOC "aspeed-soc" diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h new file mode 100644 index 0000000000..0fbb7f68be --- /dev/null +++ b/include/hw/misc/aspeed_lpc.h @@ -0,0 +1,32 @@ +/* + * ASPEED LPC Controller + * + * Copyright (C) 2017-2018 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef ASPEED_LPC_H +#define ASPEED_LPC_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_LPC "aspeed.lpc" +#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC) + +#define ASPEED_LPC_NR_REGS (0x260 >> 2) + +typedef struct AspeedLPCState { + /* <private> */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[ASPEED_LPC_NR_REGS]; + uint32_t hicr7; +} AspeedLPCState; + +#endif /* _ASPEED_LPC_H_ */ |