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| author | Alistair Francis | 2020-10-14 02:17:33 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-10-22 21:00:22 +0200 |
| commit | 38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e (patch) | |
| tree | b32fdca754d2b62043f812157b1a199075fca2fc /include | |
| parent | hw/riscv: Add a riscv_is_32_bit() function (diff) | |
| download | qemu-38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e.tar.gz qemu-38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e.tar.xz qemu-38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e.zip | |
hw/riscv: Load the kernel after the firmware
Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next aligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 46c00c4f15b42feb792090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/boot.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 2975ed1a31..0b01988727 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -25,6 +25,8 @@ bool riscv_is_32_bit(MachineState *machine); +target_ulong riscv_calc_kernel_start_addr(MachineState *machine, + target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, @@ -34,6 +36,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(const char *kernel_filename, + target_ulong firmware_end_addr, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); |