diff options
| author | LIU Zhiwei | 2021-06-24 12:50:19 +0200 |
|---|---|---|
| committer | Richard Henderson | 2021-06-29 19:04:56 +0200 |
| commit | 3d066e5d8008f8537e46f5ead37ecbdb4922a221 (patch) | |
| tree | 61f386da7c65aa5b1ddd8eb79e540ff9b84512ac /include | |
| parent | target/cris: Do not exit tb for X_FLAG changes (diff) | |
| download | qemu-3d066e5d8008f8537e46f5ead37ecbdb4922a221.tar.gz qemu-3d066e5d8008f8537e46f5ead37ecbdb4922a221.tar.xz qemu-3d066e5d8008f8537e46f5ead37ecbdb4922a221.zip | |
tcg: Add tcg_gen_vec_add{sub}16_i32
Implement tcg_gen_vec_add{sub}16_tl by adding corresponding i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20210624105023.3852-2-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/tcg/tcg-op-gvec.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index c69a7de984..9b67822f54 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -401,4 +401,17 @@ void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); +/* 32-bit vector operations. */ +void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); + +void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); + +#if TARGET_LONG_BITS == 64 +#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64 +#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64 +#else +#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32 +#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32 +#endif + #endif |