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| author | Sai Pavan Boddu | 2020-05-12 16:54:46 +0200 |
|---|---|---|
| committer | Jason Wang | 2020-06-18 15:05:51 +0200 |
| commit | 4c70e32f05fc7903185a4e9d01987ee3de2052f6 (patch) | |
| tree | 63eced1940fb741fc2bfb4778bd6c58b66023549 /include | |
| parent | net: cadence_gem: Fix irq update w.r.t queue (diff) | |
| download | qemu-4c70e32f05fc7903185a4e9d01987ee3de2052f6.tar.gz qemu-4c70e32f05fc7903185a4e9d01987ee3de2052f6.tar.xz qemu-4c70e32f05fc7903185a4e9d01987ee3de2052f6.zip | |
net: cadence_gem: Define access permission for interrupt registers
Q1 to Q7 ISR's are clear-on-read, IER/IDR registers
are write-only, mask reg are read-only.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions