diff options
| author | Cédric Le Goater | 2019-11-15 17:24:14 +0100 |
|---|---|---|
| committer | David Gibson | 2019-12-17 00:39:47 +0100 |
| commit | 516883c2f15bdd844543be218155898d06953c90 (patch) | |
| tree | 9d913306625dcdce1555674dd5d456ddd4f58b09 /include | |
| parent | ppc/pnv: Add a LPC "ranges" property (diff) | |
| download | qemu-516883c2f15bdd844543be218155898d06953c90.tar.gz qemu-516883c2f15bdd844543be218155898d06953c90.tar.xz qemu-516883c2f15bdd844543be218155898d06953c90.zip | |
ppc/xive: Record the IPB in the associated NVT
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The current code assumes that the fields of the NVT structure is
architected with the same layout of the thread interrupt context
registers. Fix this assumption and define an offset for the IPB
register backup value in the NVT.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/xive_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 55307cd153..530f232b04 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -255,6 +255,7 @@ typedef struct XiveNVT { uint32_t w2; uint32_t w3; uint32_t w4; +#define NVT_W4_IPB PPC_BITMASK32(16, 23) uint32_t w5; uint32_t w6; uint32_t w7; |