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| author | Peter Maydell | 2020-09-10 19:38:54 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-01 16:31:00 +0200 |
| commit | 51cb228a1d1c0e325b4e7dea0bfb3140d6d11422 (patch) | |
| tree | 8e4ce18682c9447df73be04a2e2b5104a7b96f38 /include | |
| parent | hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs (diff) | |
| download | qemu-51cb228a1d1c0e325b4e7dea0bfb3140d6d11422.tar.gz qemu-51cb228a1d1c0e325b4e7dea0bfb3140d6d11422.tar.xz qemu-51cb228a1d1c0e325b4e7dea0bfb3140d6d11422.zip | |
target/arm: Add ID register values for Cortex-M0
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour. These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation. We use the same
values that the Cortex-M3 does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions