diff options
| author | Cédric Le Goater | 2017-04-11 17:30:00 +0200 |
|---|---|---|
| committer | David Gibson | 2017-04-26 04:41:55 +0200 |
| commit | 5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7 (patch) | |
| tree | cf13fb73d96ffc293d8318ba8abb0ff290ba5d98 /include | |
| parent | ppc/pnv: Add support for POWER8+ LPC Controller (diff) | |
| download | qemu-5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7.tar.gz qemu-5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7.tar.xz qemu-5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7.zip | |
ppc/pnv: enable only one LPC bus
The default LPC bus of a multichip system is on chip 0. It's
recognized by the firmware (skiboot) using a "primary" property in the
device tree.
We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of
a chip and set the property directly from the machine level.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions